New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A unified framework for statistical timing analysis with coupling and multiple input switching
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A unified framework for statistical timing analysis with coupling and multiple input switching
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
Yield-Aware Cache Architectures
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
Proceedings of the 2007 international symposium on Physical design
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
Timing budgeting under arbitrary process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variation-aware task allocation and scheduling for MPSoC
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient decoupling capacitance budgeting considering operation and process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Robust gate sizing via mean excess delay minimization
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Process variation mitigation via post silicon clock tuning
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation
Proceedings of the Conference on Design, Automation and Test in Europe
Design time body bias selection for parametric yield improvement
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Evaluating statistical power optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing yield optimization by gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast estimation of timing yield bounds for process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs
Proceedings of the International Conference on Computer-Aided Design
Hardware/software approaches for reducing the process variation impact on instruction fetches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely over-constrains the system and results in solutions with excessive penalties. Statistical timing analysis and optimization have consequently emerged as a refinement of the traditional static timing approach for circuit design optimization. In this paper, we propose a statistical gate sizing methodology for timing yield improvement. We build statistical models for gate delays from library characterizations at multiple process corners and operating conditions. Statistical timing analysis is performed, which drives gate sizing for timing yield optimization. Experimental results are reported for the ISCAS and MCNC benchmarks. In addition, we provide insight into statistical properties of gate delays for a given technology library which intuitively explains when and why statistical optimization improves over static timing optimization.