Computation of the multivariate normal integral
ACM Transactions on Mathematical Software (TOMS)
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Leakage minimization of nano-scale circuits in the presence of systematic and random variations
Proceedings of the 42nd annual Design Automation Conference
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Feature Extraction: Foundations and Applications (Studies in Fuzziness and Soft Computing)
Feature Extraction: Foundations and Applications (Studies in Fuzziness and Soft Computing)
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
Proceedings of the 2007 international symposium on Physical design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A statistical framework for post-silicon tuning through body bias clustering
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design and CAD challenges in 45nm CMOS and beyond
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Victim alignment in crosstalk aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient Monte Carlo based incremental statistical timing analysis
Proceedings of the 45th annual Design Automation Conference
Modeling crosstalk in statistical static timing analysis
Proceedings of the 45th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clustering-based simultaneous task and voltage scheduling for NoC systems
Proceedings of the International Conference on Computer-Aided Design
Active learning framework for post-silicon variation extraction and test cost reduction
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Circuits designed in aggressively scaled technologies face both stringent power constraints and increased process variability. Achieving high parametric yield is a key design objective, but is complicated by the correlation between power and performance. This paper proposes a novel design time body bias selection framework for parametric yield optimization while reducing testing costs. The framework considers both inter- and intra-die variations as well as power-performance correlations. This approach uses a feature extraction technique to explore the underlying similarity between the gates for effective clustering. Once the gates are clustered, a Gaussian quadrature based model is applied for fast yield analysis and optimization. This work also introduces an incremental method for statistical power computation to further reduce the optimization complexity. The proposed framework improves parametric yield from 39% to 80% on average for 11 benchmark circuits while runtime is linear with circuit size and on the order of minutes for designs with up to 15K gates.