Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Refining switching window by time slots for crosstalk noise calculation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Statistical gate delay calculation with crosstalk alignment consideration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A unified framework for statistical timing analysis with coupling and multiple input switching
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Estimating path delay distribution considering coupling noise
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Victim alignment in crosstalk aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical interconnect metrics for physical-design optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 47th Design Automation Conference
Design time body bias selection for parametric yield improvement
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Increasing process variation in the nanometer regime motivates the use of statistical static timing analysis tools for timing verification. As device dimensions get smaller, signal integrity effects such as crosstalk noise become more significant. Therefore, it is necessary to accurately model the impact of crosstalk noise on the circuit delay. Process variations cause variability in the crosstalk alignment which leads to the variability in the delay noise. However, most of the existing approaches model delay noise as a worst-case deterministic quantity. In this work, we capture the variability of delay noise by first deriving the closed-form expressions of mean and standard deviation of the delay noise distribution. Next, we obtain the correlation information of the delay noise and use it to represent the delay noise distribution in canonical form. Delay noise, in canonical form, can easily be integrated with existing SSTA tools. We show experimental results that verify the accuracy of our approach.