Proceedings of the 37th Annual Design Automation Conference
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis of Combinational Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On Statistical Timing Analysis with Inter- and Intra-Die Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
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Proceedings of the 42nd annual Design Automation Conference
Block based statistical timing analysis with extended canonical timing model
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Interval-valued statistical modeling of oxide chemical-mechanical polishing
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Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits
Journal of Electronic Testing: Theory and Applications
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new statistical max operation for propagating skewness in statistical timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 45th annual Design Automation Conference
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Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A statistical approach for full-chip gate-oxide reliability analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Statistical static timing analysis: A survey
Integration, the VLSI Journal
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Proceedings of the 46th Annual Design Automation Conference
Accurate estimation of vector dependent leakage power in the presence of process variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph partition based path selection for testing of small delay defects
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Advanced variance reduction and sampling techniques for efficient statistical timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Hybrid modeling of non-stationary process variations
Proceedings of the 48th Design Automation Conference
Temperature aware statistical static timing analysis
Proceedings of the International Conference on Computer-Aided Design
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On the computation of criticality in statistical timing analysis
Proceedings of the International Conference on Computer-Aided Design
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Journal of Electronic Testing: Theory and Applications
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Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter- and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability distribution using a combination of device length enumeration for inter-die variation and an analytical approach for intra-die variation. We also propose a simple and effective model of spatial correlation of intra-die device length variation. The analysis is then extended to include spatial correlation. We test the proposed methods on paths from an industrial high-performance microprocessor and present comparisons with traditional path analysis which does not distinguish between inter- and intra-die variations. The characteristics of the device length distributions were obtained from measured data of 8 test chips with a total of 17688 device length measurements. Spatial correlation data was also obtained from these measurements. We demonstrate the accuracy of the proposed approach by comparing our results with Monte-Carlo simulation.