High speed CMOS design styles
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A statistical static timing analysis considering correlations between delays
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
A New Statistical Approach to Timing Analysis of VLSI Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Diagnosis of Delay Defects Using Statistical Timing Models
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An analysis of the wire-load model uncertainty problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting multicycle false paths in the performance optimization of sequential logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to the process variations and the variations of environmental factors such as supply voltage and temperature, the circuit parameters and hence the circuit performance such as delay fluctuate, and their variability and uncertainty are increasing in the deep sub-micron technology. Therefore, producing high performance digital circuits in high yield becomes difficult more and more. Various efforts have been done in order to analyze and reduce such fluctuations. Among them, statistical static timing analysis has been studied intensively in these days, which finds the distribution of the critical delay when the distribution of the delay of each element in a circuit is given. Such a statistical analysis takes probability into consideration, and is different from the conventional design style treating deterministic values only. Hence, it can be called a stochastic design style, which fits to the concept of the yield. This paper surveys the statistical static timing analysis tools, and considers the expectations of stochastic design. In the deep sub-micron technology, numerous collaborations between design and process will be needed in order to increase the yield and to shorten the time-to-market. Therefore, stochastic design style may open a new vista in the digital circuit design.