Toward stochastic design for digital circuits: statistical static timing analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we study the problem of delay defectdiagnosis based on statistical timing models. We propose a diagnosisalgorithm that can effectively utilize statistical timing informationbased upon single defect assumption. We evaluate itsperformance and its applicability to single as well as multiple defectscenarios via statistical defect injection and simulation. Witha statistical timing analysis framework developed in the past, wedemonstrate the new concept in statistical delay defect diagnosis,and discuss experimental results using benchmark circuits.