First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer Insertion Considering Process Variation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for optimal repeater insertion in pipelined interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the delay distribution of an interconnect pipeline stage and the slew distributions of all the nets in the circuit. Also, a buffer sizing and re-placement algorithm is presented to minimize the area of interconnect pipelines while meeting the delay and slew constraints. Experiments show that ignoring location dependent variation can cause a timing yield loss of 8.8% in a delay limited circuit, and the area can be improved by over 10% when the location dependent variation and residual random variation are understood and separated. Furthermore, under equivalent area, an interconnect pipeline optimized with only sizing changes may violate the slew constraint on over 50% of the nets, so location change is needed to best optimize these circuits.