Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization

Authors:
Paul Friedberg;Yu Cao;Jason Cain;Ruth Wang;Jan Rabaey;Costas Spanos
Affiliations:
University of California, Berkeley, CA;University of California, Berkeley, CA;University of California, Berkeley, CA;University of California, Berkeley, CA;University of California, Berkeley, CA;University of California, Berkeley, CA
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

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Abstract

Within-die spatial correlation of device parameter values caused by manufacturing variations [1] has a significant impact on circuit performance. Based on experimental and simulation results, we (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact on the variability of circuit performance.