Overview of gate linewidth control in the manufacture of CMOS logic chips
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Test structures for delay variability
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
IC Diagnosis Using Multiple Supply Pad IDDQs
IEEE Design & Test
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Product-representative "At speed" test structures for CMOS characterization
IBM Journal of Research and Development - Advanced silicon technology
Calibrating power supply signal measurements for process and probe card variations
DBT '04 Proceedings of the 2004 IEEE International Workshop on Defect Based Testing
Characterizing process variation in nanometer CMOS
Proceedings of the 44th annual Design Automation Conference
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The importance of within-die process variation and its impact on product yield has increased significantly with scaling. Within-die variation is typically monitored by embedding characterization circuits in product chips. In this work, we propose a minimally-invasive, low-overhead technique for characterizing within-die variation. The proposed technique monitors within-die variation by measuring quiescent (IDDQ) currents at multiple power supply ports during wafer-probe test. We show that the spatially distributed nature of power ports enables spatial observation of process variation. We demonstrate our methodology on an experimental test-chip fabricated in 65-nm technology. The measurement results show that the IDDQ currents drawn by multiple power supply ports correlate very well with the variation trends introduced by state-dependent leakage patterns.