Test structures for delay variability
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
Proceedings of the 43rd annual Design Automation Conference
A general framework for spatial correlation modeling in VLSI design
Proceedings of the 44th annual Design Automation Conference
Noninvasive leakage power tomography of integrated circuits by compressive sensing
Proceedings of the 13th international symposium on Low power electronics and design
Self-Measurement of Combinatorial Circuit Delays in FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A methodology for the characterization of process variation in NoC links
Proceedings of the Conference on Design, Automation and Test in Europe
Analyzing the impact of process variations on parametric measurements: novel models and applications
Proceedings of the Conference on Design, Automation and Test in Europe
Characterizing the impact of process variation on 45 nm NoC-based CMPs
Journal of Parallel and Distributed Computing
Proceedings of the International Conference on Computer-Aided Design
A new uncertainty budgeting based method for robust analog/mixed-signal design
Proceedings of the 49th Annual Design Automation Conference
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
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Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of ICs from their designers' original intent. These deviations reduce the parametric yield and revenues from integrated circuit fabrication. In this paper we provide a complete treatment to the subject of within-die variations. We propose a scan-chain based system, vMeter, to extract within-die variations in an automated fashion. We implement our system in a sample of 90nm chips, and collect the within-die variations data. Then we propose a number of novel statistical analysis techniques that accurately model the within-die variation trends and capture the spatial correlations. We propose the use of maximum-likelihood techniques to find the required parameters to fit the model to the data. The accuracy of our models is statistically verified through residual analysis and variograms. Using our successful modeling technique, we propose a procedure to generate synthetic within-die variation patterns that mimic, or imitate, real silicon data.