A methodology for the characterization of process variation in NoC links

Authors:
Carles Hernández;Federico Silla;José Duato
Affiliations:
Universidad Politécnica de Valencia, Camino de Vera s/n Valencia, España;Universidad Politécnica de Valencia, Camino de Vera s/n Valencia, España;Universidad Politécnica de Valencia, Camino de Vera s/n Valencia, España
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2010

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Abstract

Associated with the ever growing integration scales is the increase in process variability. In the context of network-on-chip, this variability affects the maximum frequency that could be sustained by each link that interconnects two cores in a chip multiprocessor. In this paper we present a methodology to model delay variations in NoC links. We also show its application to several technologies, namely 45nm, 32nm, 22nm, and 16nm. Simulation results show that conclusions about variability greatly depend on the implementation context.