Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Process variation aware cache leakage management
Proceedings of the 2006 international symposium on Low power electronics and design
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Yield-Aware Cache Architectures
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A New Simulation Method for NBTI Analysis in SPICE Environment
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Modeling of PMOS NBTI Effect Considering Temperature Variation
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
Variation resilient low-power circuit design methodology using on-chip phase locked loop
Proceedings of the 44th annual Design Automation Conference
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Penelope: The NBTI-Aware Processor
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning
Proceedings of the 2009 International Conference on Computer-Aided Design
A multi-level approach to reduce the impact of NBTI on processor functional units
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Aging-resilient design of pipelined architectures using novel detection and correction circuits
Proceedings of the Conference on Design, Automation and Test in Europe
M-IVC: Applying multiple input vectors to co-optimize aging and leakage
Microelectronics Journal
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture
Proceedings of the 50th Annual Design Automation Conference
Enhancing NBTI recovery in SRAM arrays through recovery boosting
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NBTI mitigation by optimized NOP assignment and insertion
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Parametric variation introduced by nano-scale device fabrication inaccuracy can exacerbate the PMOS transistor wear-out problem and further reduce the reliable lifetime of microprocessors. In this work, we propose microarchitecture design techniques to combat the combined effect of NBTI and process variation (PV) on the reliability of high-performance microprocessors. Experimental evaluation shows our proposed process variation aware (PV-aware) NBTI tolerant microarchitecture design techniques can considerably improve the lifetime of reliability operation while achieving an attractive trade-off with performance and power.