A physical alpha-power law MOSFET model
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
The M5 Simulator: Modeling Networked Systems
IEEE Micro
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Penelope: The NBTI-Aware Processor
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
IBM Journal of Research and Development
Facelift: Hiding and slowing down aging in multicores
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
NBTI tolerant microarchitecture design in the presence of process variation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
A multi-level approach to reduce the impact of NBTI on processor functional units
Proceedings of the 20th symposium on Great lakes symposium on VLSI
The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
A linear programming approach for minimum NBTI vector selection
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Aging-aware compiler-directed VLIW assignment for GPGPU architectures
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
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Negative Bias Temperature Instability (NBTI) is a major source of transistor aging in scaled CMOS, resulting in slower devices and shorter lifetime. NBTI is strongly dependent on the input vector. Moreover, a considerable fraction of execution time of an application is spent to execute NOP (No Operation) instructions. Based on these observations, we present a novel NOP assignment to minimize NBTI effect, i.e. maximum NBTI relaxation, on the processors. Our analysis shows that NBTI degradation is more impacted by the source operands rather than instruction opcodes. Given this, we obtain the instruction, along with the operands, with minimal NBTI degradation, to be used as NOP. We also proposed two methods, software-based and hardware-based, to replace the original NOP with this maximum aging reduction NOP. Experimental results based on SPEC2000 applications running on a MIPS processor show that this method can extend the lifetime by 37% in average while the overhead is negligible.