Lifetime Reliability: Toward an Architectural Solution

Authors:
Jayanth Srinivasan;Sarita V. Adve;Pradip Bose;Jude A. Rivers
Affiliations:
University of Illinois, Urbana-Champaign;-;-;-
Venue:
IEEE Micro
Year:
2005

Citing 10
Cited 24

Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture
Probability and Statistics with Reliability, Queuing and Computer Science Applications

Probability and Statistics with Reliability, Queuing and Computer Science Applications
Joint local and global hardware adaptations for energy

Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors

Computer
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic

DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Temperature-aware microarchitecture

Proceedings of the 30th annual international symposium on Computer architecture
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
The Case for Lifetime Reliability-Aware Microprocessors

Proceedings of the 31st annual international symposium on Computer architecture
The Impact of Technology Scaling on Lifetime Reliability

DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Exploiting Structural Duplication for Lifetime Reliability Enhancement

Proceedings of the 32nd annual international symposium on Computer Architecture

Interactive presentation: Improving the fault tolerance of nanometric PLA designs

Proceedings of the conference on Design, automation and test in Europe
Reliability-aware design for nanometer-scale devices

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors

Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems
ESL power analysis of embedded processors for temperature and reliability estimations

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Characterizing processor thermal behavior

Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Power-efficient, reliable microprocessor architectures: modeling and design methods

Proceedings of the 20th symposium on Great lakes symposium on VLSI
System-level reliability modeling for MPSoCs

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Combating Aging with the Colt Duty Cycle Equalizer

MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Reliability, thermal, and power modeling and optimization

Proceedings of the International Conference on Computer-Aided Design
UniFI: leveraging non-volatile memories for a unified fault tolerance and idle power management technique

Proceedings of the 26th ACM international conference on Supercomputing
A systematic methodology for reliability improvements on SoC-based software defined radio systems

VLSI Design
PGCapping: exploiting power gating for power capping and core lifetime balancing in CMPs

Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Thermal Aware Processor Operation Point Management

UCC '12 Proceedings of the 2012 IEEE/ACM Fifth International Conference on Utility and Cloud Computing
A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

Analog Integrated Circuits and Signal Processing
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults

MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
On the Simulation of HCI-Induced Variations of IC Timings at High Level

Journal of Electronic Testing: Theory and Applications
Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification

Proceedings of the Conference on Design, Automation and Test in Europe
System-level modeling and microprocessor reliability analysis for backend wearout mechanisms

Proceedings of the Conference on Design, Automation and Test in Europe
Employing circadian rhythms to enhance power and reliability

ACM Transactions on Design Automation of Electronic Systems (TODAES)
NBTI mitigation by optimized NOP assignment and insertion

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Mitigating lifetime underestimation: a system-level approach considering temperature variations and correlations between failure mechanisms

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A 'cool' way of improving the reliability of HPC machines

SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Reliability aware dynamic voltage and frequency scaling for improved microprocessor lifetime

ACM SIGOPS Operating Systems Review
A column parity based fault detection mechanism for FIFO buffers

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

As scaling threatens to erode reliability standards, lifetime reliability must become a first-class design constraint. Microarchitectural intervention offers a novel way to manage lifetime reliability without significantly sacrificing cost and performance.