Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Procrastinating voltage scheduling with discrete frequency sets
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Dynamic voltage frequency scaling for multi-tasking systems using online learning
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Temperature-aware voltage selection for energy optimization
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems
Proceedings of the 46th Annual Design Automation Conference
Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems
ACM SIGBED Review - Work-in-Progress (WiP) Session of the 23rd Euromicro Conference on Real-Time Systems (ECRTS 2011)
Optimal intratask dynamic voltage-scaling technique and its practical extensions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TALk: A Temperature-Aware Leakage Minimization Technique for Real-Time Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Existing schemes for dynamic voltage and frequency scaling (DVFS) do not account for the intertask thermal cycles. The chip reliability testing process usually also is not inclusive of test cases quantifying the chip reliability in the presence of small scale thermal cycles. However, a good number of in-field chip failures are attributed to the consequences of thermal cycles. Thus, it is imperative to include their effects into the processor voltage and frequency selection process. Our work focuses on developing an integrated processor thermal and performance management system centered on novel polynomial time scheduling algorithms that achieve minimal thermal cycle guarantees in soft real time environments. Our scheme leverages application awareness and runtime monitoring for improving the lifetime of the chip, while achieving considerable energy savings. Our scheme shows a significant reduction in thermal cycles and peaks, leading to longer chip life expectations. Our results indicate a 10 fold increase in the expected chip lifetime and 50% energy savings compared to operation at the rated maximum voltage and frequency.