Procrastinating voltage scheduling with discrete frequency sets
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Dynamic voltage frequency scaling for multi-tasking systems using online learning
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Temperature-aware voltage selection for energy optimization
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems
DEPEND '09 Proceedings of the 2009 Second International Conference on Dependability
Proceedings of the 46th Annual Design Automation Conference
System-level power management using online learning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of reliability and power consumption in systems on a chip
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
TALk: A Temperature-Aware Leakage Minimization Technique for Real-Time Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Dynamic voltage and frequency scaling (DVFS) is heavily used for power management in real-time environments. Although the schemes leveraging DVFS provide significant power reduction, adverse effects on chip reliability are possible. Alternate increase and decrease in operating voltage and frequency leads to thermal cycling. Increasing transistor packing density leads to a larger range of possible operating temperatures, exacerbating the thermal cycling problem. Also, the chip reliability quantification process does not include and represent the effects of small scale thermal cycles. A good number of in-field chip failures are attributed to the consequences of these. Thus, it is imperative to include their effects into the processor voltage and frequency selection process. Our work develops an integrated processor thermal and performance management technique centered on novel polynomial time scheduling algorithms that lead to lowering of thermal cycles in soft real time environments. Our technique leverages application awareness and runtime monitoring for improving chip lifetime, while achieving considerable energy savings. We show that a significant reduction in thermal cycles and peaks is possible, leading to longer chip life expectations.