Dynamic power management in a mobile multimedia system with guaranteed quality-of-service
Proceedings of the 38th annual Design Automation Conference
Predictive dynamic thermal management for multimedia applications
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Trading off Reliability and Power-Consumption in Ultra-Low Power Systems
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Managing Power Consumption in Networks on Chip
Proceedings of the conference on Design, automation and test in Europe
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Exploiting Microarchitectural Redundancy For Defect Tolerance
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Reliability and Power Management of Integrated Systems
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Performance-Related Reliability Measures for Computing Systems
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simulation methodology for reliability analysis in multi-core SoCs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Temperature-aware MPSoC scheduling for reducing hot spots and gradients
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A tool flow for predicting system level timing failures due to interconnect reliability degradation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Reliability aware dynamic voltage and frequency scaling for improved microprocessor lifetime
ACM SIGOPS Operating Systems Review
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Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature, have made reliability assessment a much more significant issue in design. Although reliability of devices and interconnect has been broadly studied, here we characterize reliability at the system level. Thus we consider component-based System on Chip designs. Reliability is strongly affected by system temperature, which is in turn driven by power consumption. Thus, component reliability and their power management should be addressed jointly. We present here a joint reliability and power management optimization problem whose solution is an optimal management policy. When careful joint policy optimization is performed, we obtain a significant improvement in energy consumption (40%) in tandem with meeting reliability constraint for all operating temperatures.