A simulation methodology for reliability analysis in multi-core SoCs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A Framework for Architecture-Level Lifetime Reliability Modeling
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Optimization of reliability and power consumption in systems on a chip
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A temperature-aware time-dependent dielectric breakdown analysis framework
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
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The continuous scaling of feature dimensions and the introduction of new dielectric materials is pushing the interconnects closer to their reliability limits. Degradation mechanisms are becoming more pronounced, making the interconnect lifetime a challenge at the level of process qualification. Moreover, these mechanisms exhibit new properties, like gradual degradation of electrical parameters instead of abrupt breakdowns phenomena. As a result, it becomes more likely that systems will fail because one of their transistors or wires becomes gradually too slow. These soft failures are not captured by existing tools. The methodology introduced in this paper estimates the impact of two dominant interconnect degradation mechanisms (EM & TDDB) on the total system performance. This constitutes a first step toward system level driven reliability aware design.