A Framework for Architecture-Level Lifetime Reliability Modeling

Authors:
Jeonghee Shin;Victor Zyuban;Zhigang Hu;Jude A. Rivers;Pradip Bose
Affiliations:
IBM T.J. Watson Research Center, USA;IBM T.J. Watson Research Center, USA;IBM T.J. Watson Research Center, USA;IBM T.J. Watson Research Center, USA;IBM T.J. Watson Research Center, USA
Venue:
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Year:
2007

Citing 0
Cited 15

A tool flow for predicting system level timing failures due to interconnect reliability degradation

Proceedings of the 18th ACM Great Lakes symposium on VLSI
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Electromigration for microarchitects

ACM Computing Surveys (CSUR)
Thermal analysis of multiprocessor SoC applications by simulation and verification

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-efficient, reliable microprocessor architectures: modeling and design methods

Proceedings of the 20th symposium on Great lakes symposium on VLSI
AgeSim: a simulation framework for evaluating the lifetime reliability of processor-based SoCs

Proceedings of the Conference on Design, Automation and Test in Europe
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms

Proceedings of the Conference on Design, Automation and Test in Europe
Robust embedded software design through early analysis of quality faults

Proceedings of the 4th India Software Engineering Conference
Characterizing the lifetime reliability of manycore processors with core-level redundancy

Proceedings of the International Conference on Computer-Aided Design
Using implications to choose tests through suspect fault identification

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Reliability-Aware Proactive Energy Management in Hard Real-Time Systems: A Motivational Case Study

International Journal of Adaptive, Resilient and Autonomic Systems
Systematic Design Principles for Cost-Effective Hard Constraint Management in Dynamic Nonlinear Systems

International Journal of Adaptive, Resilient and Autonomic Systems
On the Simulation of HCI-Induced Variations of IC Timings at High Level

Journal of Electronic Testing: Theory and Applications
Use it or lose it: wear-out and lifetime in future chip multiprocessors

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Unified reliability estimation and management of NoC based chip multiprocessors

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper tackles the issue of modeling chip lifetime reliability at the architecture level. We propose a new and robust structure-aware lifetime reliability model at the architecture-level, where devices only vulnerable to failure mechanisms and the effective stress condition of these devices are taken into account for the failure rate of microarchitecture structures. In addition, we present this reliability analysis framework based on a new concept, called the FIT of reference circuit or FORC, which allows architects to quantify failure rates without having to delve into low-level circuit- and technology-specific details of the implemented architecture. This is done through a onetime characterization of a reference circuit needed to quantify the reference FITs for each class of modeled failure mechanisms for a given technology and implementation style. With this new reliability modeling framework, architects are empowered to proceed with architecture-level reliability analysis independent of technological and environmental parameters.