Probability and statistics with reliability, queuing and computer science applications
Probability and statistics with reliability, queuing and computer science applications
A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers
IEEE Transactions on Computers
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
Computing System Reliability: Models And Analysis
Computing System Reliability: Models And Analysis
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Proceedings of the 32nd annual international symposium on Computer Architecture
A Framework for Architecture-Level Lifetime Reliability Modeling
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Amdahl's Law in the Multicore Era
Computer
On Modeling the Lifetime Reliability of Homogeneous Manycore Systems
PRDC '08 Proceedings of the 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing
Facelift: Hiding and slowing down aging in multicores
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
High-Speed VLSI Interconnections
High-Speed VLSI Interconnections
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
Proceedings of the Conference on Design, Automation and Test in Europe
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture
Proceedings of the 50th Annual Design Automation Conference
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A hybrid packet-circuit switched router for optical network on chip
Computers and Electrical Engineering
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With aggressive technology scaling, integrated circuits suffer from ever-increasing wearout effects and their lifetime reliability has become a serious concern for the industry. For manycore processors that integrate a large number of processor cores on a single silicon die, introducing core-level redundancy is an effective way to alleviate this problem. There are, however, many strategies to make use of the redundant cores, which have different implications on the aging effects of embedded processors. How to characterize the lifetime reliability of manycore processors with different usages is therefore an important and relevant problem. In this paper, we propose a novel analytical method to tackle the above problem, which captures the impact of workloads and the associated temperature variations. We then use the proposed model to analyze the lifetime reliability for manycore processors with various redundancy configurations. Finally, the effectiveness of the proposed method is demonstrated with extensive experiments.