Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
On the Design of a Photonic Network-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
System level assessment of an optical NoC in an MPSoC platform
Proceedings of the conference on Design, automation and test in Europe
ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Analysis of challenges for on-chip optical interconnects
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
UNION: a unified inter/intra-chip optical network for chip multiprocessors
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Characterizing the lifetime reliability of manycore processors with core-level redundancy
Proceedings of the International Conference on Computer-Aided Design
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The increasing number of Intellectual Property (IP) cores challenges the traditional electrical Network on Chip (NoC). Silicon nanophotonics becomes a leading technology because of offering several benefits for NoC. Also, On-chip services, including guaranteed service and best-effort service, have different traffic characteristics. This has an important influence on the performance of NoC. This paper proposes a hybrid packet-circuit switched router for optical Network on Chip (ONoC). It can support optical circuit switching (OCS) and optical packet switching (OPS) in parallel and simultaneously, in order to optimize the performance of the network with both services. According to the simulation results, the proposed architecture achieves lower latency and higher throughput than the traditional architectures in the same network scale.