The sun fireplane system interconnect
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance
WOMPAT '01 Proceedings of the International Workshop on OpenMP Applications and Tools: OpenMP Shared Memory Parallel Programming
Token coherence: decoupling performance and correctness
Proceedings of the 30th annual international symposium on Computer architecture
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Light speed arbitration and flow control for nanophotonic interconnects
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
An intra-chip free-space optical interconnect
Proceedings of the 37th annual international symposium on Computer architecture
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
Proceedings of the 37th annual international symposium on Computer architecture
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
A hybrid packet-circuit switched router for optical network on chip
Computers and Electrical Engineering
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Hi-index | 0.00 |
On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfers, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article analyzes on-chip communication challenges and studies the characteristics of existing electrical and emerging nanophotonic interconnect. Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network, is thus introduced. Iris's circuit-switched subnetwork supports throughput-sensitive data transfer. Iris's optical-antenna-array-based broadcast--multicast subnetwork optimizes latency-critical traffic and supports the path setup of circuit-switched communication. Overall, the proposed nanophotonic network design offers an on-chip communication backplane that is power efficient while demonstrating low latency and high throughput.