On-Chip Interconnection Networks of the TRIPS Chip

Authors:
Paul Gratz;Changkyu Kim;Karthikeyan Sankaralingam;Heather Hanson;Premkishore Shivakumar;Stephen W. Keckler;Doug Burger
Affiliations:
The University of Texas at Austin;Intel;University of Wisconsin-Madison;IBM;The University of Texas at Austin;The University of Texas at Austin;The University of Texas at Austin
Venue:
IEEE Micro
Year:
2007

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Abstract

The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. Our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.