A high-performance low-power nanophotonic on-chip network

Authors:
Zheng Li;Jie Wu;Li Shang;Alan R. Mickelson;Manish Vachharajani;Dejan Filipovic;Wounjhang Park;Yihe Sun
Affiliations:
Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;University of Colorado, Boulder, CO, USA;University of Colorado, Boulder, CO, USA;University of Colorado, Boulder, CO, USA;University of Colorado, Boulder, CO, USA;University of Colorado, Boulder, CO, USA;Tsinghua University, Beijing, China
Venue:
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Year:
2009

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Abstract

On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article presents Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network. Iris' linear-waveguide-based throughput-optimized circuit-switched subnetwork supports throughput-sensitive data transfer. Iris' planar-waveguide-based WDM broadcast-multicast subnetwork optimizes latency-critical traffic and supports the circuit setup of circuit-switched communication. Overall, the proposed design delivers an on-chip communication backplane with high power efficiency, low latency, and excellent throughput.