A high-performance low-power nanophotonic on-chip network
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Analysis of photonic networks for a chip multiprocessor using scientific applications
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Spectrum: a hybrid nanophotonic-electric on-chip network
Proceedings of the 46th Annual Design Automation Conference
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
Proceedings of the 37th annual international symposium on Computer architecture
Crosstalk noise and bit error rate analysis for optical network-on-chip
Proceedings of the 47th Design Automation Conference
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Enabling quality-of-service in nanophotonic network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Journal of Parallel and Distributed Computing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 48th Design Automation Conference
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs
Proceedings of the First International Workshop on Many-core Embedded Systems
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The Network-on-Chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-on chip(SoC) and chip multiprocessors (CMP). In future high performance CMPs, however, the high bandwidth requirements will not be adequately provided by electronic NoCs without dissipating large amounts of power. Previously, we have made the case for the photonic NoC as a unique interconnect solution for delivering scalable bandwidth-per-watt performance that surpasses equivalent electronic NoCs. Building on this work, we study the adoption of photonic communication for CMPs and we present three main contributions: (1) we propose two nonblocking topologies for photonic NoC designs and we assess both qualitatively and quantitatively the pros and cons that they offer with respect to the original (blocking) topology, (2) we show how a photonic NoC is better suited for a CMP made of complex multi-threaded cores, and (3) we present the first simulation based assessment of the benefits of using a photonic NoC for a real application, i.e. computing a large FFT.