Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Analysis of challenges for on-chip optical interconnects
Proceedings of the 19th ACM Great Lakes symposium on VLSI
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture
Proceedings of the 11th international workshop on System level interconnect prediction
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Power-efficient variation-aware photonic on-chip network management
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Global On-Chip Coordination at Light Speed
IEEE Design & Test
PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks
Proceedings of the Conference on Design, Automation and Test in Europe
On-chip interconnect analysis of performance and energy metrics under different design goals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliability Modeling and Management of Nanophotonic On-Chip Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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The nanophotonic network promises improved communications between cores in many-core systems. This paper discusses a novel modeling and simulation methodology. This infrastructure can compare performance, power consumption and reliability of nanophotonic network designs. Phenomenologically determined transfer-matrix device models are employed to characterize network performance under realistic multi-threaded applications, optical power transmission across the full wevelength-division multiplexing spectrum, and network reliability as affected by fabrication-induced process variation and run-time system thermal effects. Five recently proposed networks are analyzed to better elucidate advantages and limitations.