Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Analysis of challenges for on-chip optical interconnects
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Light speed arbitration and flow control for nanophotonic interconnects
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
Proceedings of the 37th annual international symposium on Computer architecture
Crosstalk noise and bit error rate analysis for optical network-on-chip
Proceedings of the 47th Design Automation Conference
Power-efficient variation-aware photonic on-chip network management
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Addressing system-level trimming issues in on-chip nanophotonic networks
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Proceedings of the 48th Design Automation Conference
Reliability Modeling and Management of Nanophotonic On-Chip Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Recent advances in silicon photonic device and fabrication technologies make silicon photonic interconnect a promising communication fabric to address the inter-core and inter-die interconnect challenges for future embedded many-core processors. Informed design decisions in silicon photonic interconnection require optimization of performance, power efficiency, and reliability for different application scenarios. Optimizing these network and system metrics require understanding of silicon photonics device characteristics. However, existing design space exploration methodologies rely on time-consuming electromagnetic simulations or measurement of fabricated devices. In this paper, we introduce analytical models of devices, explore their design spaces, and apply them to different applications. The analytical models consist of parametrized transfer-matrices, with parameters categorized as fabrication-induced parameters and design parameters. Fabrication-induced parameters can be calibrated against measurements of fabricated devices to achieve high accuracy, whereas design parameters help in extrapolating the device characteristics. We develop and calibrate analytical models of widely used passive and doped micro-ring resonators. Three case studies of silicon photonic interconnects are discussed to represent different embedded applications and quantify the design trade-offs including performance requirements, power efficiency, and reliability constraints from the network system level.