Proceedings of the 48th Design Automation Conference
Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Tolerating process variations in nanophotonic on-chip networks
Proceedings of the 39th Annual International Symposium on Computer Architecture
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
System-level modeling and analysis of thermal effects in optical networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-efficient calibration and reconfiguration for on-chip optical communication
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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While transistor performance and energy efficiency have dramatically improved in recent years, electrical interconnect improvements has failed to keep pace. Recent advances in nanophotonic fabrication have made on-chip optics an attractive alternative. However, system integration challenges remain. In particular, the parameters of on-chip nanophotonic structures are sensitive to fabrication-induced process variation and run-time spatial thermal variation across the die. This work addresses the performance and reliability challenges that arise from this sensitivity to variation. The paper first presents a model predicting the system-level effects of thermal and process variation in nanophotonic networks. It then shows how to optimize many-core system performance and reliability by using run-time techniques to compensate for the thermal and process variation effects.