The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
SPEED DMON: cache coherence on an optical multichannel interconnect architecture
Journal of Parallel and Distributed Computing - Special issue on parallel computing with optical interconnects
OPTNET: a cost-effective optical network for multiprocessors
ICS '98 Proceedings of the 12th international conference on Supercomputing
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Optical networks: a practical perspective
Optical networks: a practical perspective
ZOMA: A Preemptive Deadlock Recovery Mechanism for Fully Adaptive Routing in Wormhole Networks
ICCNMC '01 Proceedings of the 2001 International Conference on Computer Networks and Mobile Computing (ICCNMC'01)
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Current-mode signaling in deep submicrometer global interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
High-Speed Optoelectronics Receivers in SiGe
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Optical solutions for system-level interconnect
Proceedings of the 2004 international workshop on System level interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predictions of CMOS compatible on-chip optical interconnect
Proceedings of the 2005 international workshop on System level interconnect prediction
A novel buffer circuit for energy efficient signaling in dual-VDD systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
CMOS Photonics for High-Speed Interconnects
IEEE Micro
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
Performance Evaluation for Three-Dimensional Networks-On-Chip
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
The case for low-power photonic networks on chip
Proceedings of the 44th annual Design Automation Conference
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
RF interconnects for communications on-chip
Proceedings of the 2008 international symposium on Physical design
ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
IEEE Transactions on Computers
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
A High-Speed Optical Multi-Drop Bus for Computer Interconnections
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Analysis of challenges for on-chip optical interconnects
Proceedings of the 19th ACM Great Lakes symposium on VLSI
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture
Proceedings of the 11th international workshop on System level interconnect prediction
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Spectrum: a hybrid nanophotonic-electric on-chip network
Proceedings of the 46th Annual Design Automation Conference
Serial-link bus: a low-power on-chip bus architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
Proceedings of the 37th annual international symposium on Computer architecture
A multilayer nanophotonic interconnection network for on-chip many-core communications
Proceedings of the 47th Design Automation Conference
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
OPAL: a multi-layer hybrid photonic NoC for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Large-scale integrated photonics for high-performance interconnects
ACM Journal on Emerging Technologies in Computing Systems (JETC)
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BLOCON: a bufferless photonic Clos Network-on-Chip architecture
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Reliability Modeling and Management of Nanophotonic On-Chip Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
With increasing application complexity and improvements in process technology, Chip MultiProcessors (CMPs) with tens to hundreds of cores on a chip are becoming a reality. Networks-on-Chip (NoCs) have emerged as scalable communication fabrics that can support high bandwidths for these massively parallel multicore systems. However, traditional electrical NoC implementations still need to overcome the challenges of high data transfer latencies and large power consumption. On-chip photonic interconnects with high performance-per-watt characteristics have recently been proposed as an alternative to address these challenges for intra-chip communication. In this article, we explore using low-cost photonic interconnects on a chip to enhance traditional electrical NoCs. Our proposed hybrid photonic ring-mesh NoC (METEOR) utilizes a configurable photonic ring waveguide coupled to a traditional 2D electrical mesh NoC. Experimental results indicate a strong motivation to consider the proposed architecture for future CMPs, as it can provide about 5× reduction in power consumption and improved throughput and access latencies, compared to traditional electrical 2D mesh and torus NoC architectures. Compared to other previously proposed hybrid photonic NoC fabrics such as the hybrid photonic torus, Corona, and Firefly, our proposed fabric is also shown to have lower photonic area overhead, power consumption, and energy-delay product, while maintaining competitive throughput and latency.