On the Design of a Photonic Network-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
The case for low-power photonic networks on chip
Proceedings of the 44th annual Design Automation Conference
ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
OPAL: a multi-layer hybrid photonic NoC for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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This paper focuses on the investigation of integratedCMOS and Silicon/Germanium (SiGe) devices for high-speedoptical receiver circuits. In this paper, we presentseveral competitive designs of front-end transimpedanceamplifiers (TIA) for optical receiver applications using theIBM 5HP (0.5micron) SiGe technology. This technologyexhibits fT and fMAX of 47GHz and 65GHz respectively.Spectre simulations in the Cadence Affirma analog designenvironment are conducted for both the TIA's and acomplete receiver circuit consisting of a TIA, a cascadedmulti-stage differential amplifier and a multi-stageinverting amplifier at the single supply voltage of 3.3V. Wealso discuss the practicality of using SiGe basedphotodetectors for 1.3-1.5um wavelength light and the useof Neolinear's NeoCircuit/NeoCell mixed signal designtools for optimization of the analog circuits.