Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Optical networks: a practical perspective
Optical networks: a practical perspective
Coping with Latency in SOC Design
IEEE Micro
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
High-Speed Optoelectronics Receivers in SiGe
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Proceedings of the 32nd annual international symposium on Computer Architecture
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
CMOS Photonics for High-Speed Interconnects
IEEE Micro
Trends toward on-chip networked microsystems
International Journal of High Performance Computing and Networking
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
The case for low-power photonic networks on chip
Proceedings of the 44th annual Design Automation Conference
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture
Proceedings of the 11th international workshop on System level interconnect prediction
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Hybrid modeling of opto-electrical interfaces using DEVS and modelica
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
XY-turn model for deadlock free routing in honeycomb networks-on-chip
APCC'09 Proceedings of the 15th Asia-Pacific conference on Communications
An intra-chip free-space optical interconnect
Proceedings of the 37th annual international symposium on Computer architecture
An insertion loss balance aware routing scheme in photonic network on chip
ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing
A multilayer nanophotonic interconnection network for on-chip many-core communications
Proceedings of the 47th Design Automation Conference
PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Enabling quality-of-service in nanophotonic network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors
ACM Journal on Emerging Technologies in Computing Systems (JETC)
F2BFLY: an on-chip free-space optical network with wavelength-switching
Proceedings of the international conference on Supercomputing
BLOCON: a bufferless photonic Clos Network-on-Chip architecture
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
The role of optics in future high radix switch design
Proceedings of the 38th annual international symposium on Computer architecture
Enhancing effective throughput for transmission line-based bus
Proceedings of the 39th Annual International Symposium on Computer Architecture
Scalable architecture for a contention-free optical network on-chip
Journal of Parallel and Distributed Computing
Proceedings of the Fifth International Workshop on Network on Chip Architectures
Packet switching optical network-on-chip architectures
Computers and Electrical Engineering
Proceedings of the Conference on Design, Automation and Test in Europe
System-level modeling and analysis of thermal effects in optical networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid packet-circuit switched router for optical network on chip
Computers and Electrical Engineering
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Journal of Systems Architecture: the EUROMICRO Journal
Towards a scalable, low-power all-optical architecture for networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Recent remarkable advances in nanoscale silicon-photonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the unique capabilities of optical technologies in the on-chip communications infrastructure. Based on these nano-photonic building blocks, we consider a photonic network-on-chip architecture designed to exploit the enormous transmission bandwidths, low latencies, and low power dissipation enabled by data exchange in the optical domain. The novel architectural approach employs a broadband photonic circuit-switched network driven in a distributed fashion by an electronic overlay control network which is also used for independent exchange of short messages. We address the critical network design issues for insertion in chip multiprocessors (CMP) applications, including topology, routing algorithms, path-setup and teardown procedures, and deadlock avoidance. Simulations show that this class of photonic networks-on-chip offers a significant leap in the performance for CMP intrachip communication systems delivering low-latencies and ultra-high throughputs per core while consuming minimal power.