Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
On the Design of a Photonic Network-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
System level assessment of an optical NoC in an MPSoC platform
Proceedings of the conference on Design, automation and test in Europe
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Photonic NoC for DMA Communications in Chip Multiprocessors
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Optical Networks: A Practical Perspective, 3rd Edition
Optical Networks: A Practical Perspective, 3rd Edition
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Architectures and routing schemes for optical network-on-chips
Computers and Electrical Engineering
A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
An intra-chip free-space optical interconnect
Proceedings of the 37th annual international symposium on Computer architecture
A multilayer nanophotonic interconnection network for on-chip many-core communications
Proceedings of the 47th Design Automation Conference
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Computers and Electrical Engineering
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In this paper we propose three packet switching optical network-on-chip architectures, i.e., TON-I, TON-II and TON-III. Micro-ring resonator (MRR)-based optical switches are adopted for wavelength-based routing in TONs. Direct optical channels (DOCs) are introduced as the direct optical paths between nodes. For each node in TON-I, II, and III, the number of DOCs is 4, 8, and 10 respectively. We present the implementations of a packet switching optical NoC with TONs with a limited number of wavelengths. The design of routers and schema for wavelength assignment are presented for each TON. The number of different wavelengths needed for in TON-I, II, and III is 2, 4, and 6. The proposed architectures yield highly scalabilities, high bandwidth, low latency and low power consumption. TON network performances are evaluated by simulation as presented. The transmission power loss analysis is provided as well. Simulation and analysis results show that the proposed architectures can be considered as a viable solution for future NoCs.