Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
On the Design of a Photonic Network-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Analysis of challenges for on-chip optical interconnects
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Enabling quality-of-service in nanophotonic network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
F2BFLY: an on-chip free-space optical network with wavelength-switching
Proceedings of the international conference on Supercomputing
Two-hop free-space based optical interconnects for chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Packet switching optical network-on-chip architectures
Computers and Electrical Engineering
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
| Hi-index | 0.00 |
Multi-core chips or chip multiprocessors (CMPs) are becoming the de facto architecture for scaling up performance and taking advantage of the increasing transistor count on the chip within reasonable power consumption levels. The projected increase in the number of cores in future CMPs is putting stringent demands on the design of the on-chip network (or network-on-chip, NOC). Nanophotonic interconnects have recently emerged as a viable alternate technology solution for the design of NOC because of their higher communication bandwidth, much reduced power consumption and wiring simplification. Several photonic NOC approaches have recently been proposed. A common feature of almost all of these approaches is the integration of the entire optical network onto a single silicon waveguide layer. However, keeping the entire network on a single layer has a serious implication for power losses and design complexity due to the large amount of waveguide crossings. In this paper, we propose MPNOC: a multilayer photonic networks-on-chip. MPNOC combines the recent advances in silicon photonics and three-dimensional (3D) stacking technology with architectural innovations in an integrated architecture that provides ample bandwidth, low latency, and energy efficient on-chip communications for future CMPs. Simulation results show MPNOC can achieve 81.92 TFLOP/s peak bandwidth and an energy savings up to 23% compared to other proposed planar photonic NOC architectures.