Predictions of CMOS compatible on-chip optical interconnect

Authors:
Guoqing Chen;Hui Chen;Mikhail Haurylau;Nicholas A. Nelson;David H. Albonesi;Philippe M. Fauchet;Eby G. Friedman
Affiliations:
Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA;Department of Physics and Astronomy, University of Rochester, Rochester, NY 14627, USA;Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA;Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA;School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853, USA;Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA;Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA
Venue:
Integration, the VLSI Journal
Year:
2007

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Abstract

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22nm technology node.