Proceedings of the 2004 international workshop on System level interconnect prediction
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Accurate capture of timing parameters in inductively-coupled on-chip interconnects
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
Exact distribution of the max/min of two Gaussian random variables
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new high-speed interconnect crosstalk fault model and compression for test space
WSEAS TRANSACTIONS on COMMUNICATIONS
Test pattern generation for crosstalk fault of high-speed interconnect
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switch-factor based loop RLC modeling for efficient timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
/sup A/ new approach to handle inductance effects for multiple signal lines is presented. The worst-case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (L/sub eff/) for multiple lines. Based on a look-up table for L/sub eff/, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlists for multiple lines, this approach greatly improves the computational efficiency and maintains accuracy for timing and signal integrity analysis. We apply these models to repeater insertion in critical paths and find that, for a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC models.