Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Slope propagation in static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple metric for slew rate of RC circuits based on two circuit moments
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
Exact distribution of the max/min of two Gaussian random variables
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip optical interconnect for reduced delay uncertainty
Proceedings of the 2nd international conference on Nano-Networks
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation
Microelectronics Journal
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Timing uncertainty caused by inductive and capacitive coupling is one of the major bottlenecks in timing analysis. In this paper, we propose an effective loop RLC modeling technique to efficiently decouple lines with both inductive and capacitive coupling. We generalize the RLC decoupling problem based on the theory of distributed RLC lines and a switch-factor, which is the voltage ratio between two nets. This switch-factor is also known as the Miller factor, and is widely used to model capacitive coupling. The proposed modeling technique can be directly applied to partial RLC netlists extracted using existing parasitic extraction tools without advance knowledge of the return path. The new model captures the impact of neighboring switching activity as it significantly affects the current return path. As demonstrated in our experiments, the new model accurately predicts both upper and lower delay bounds as a function of neighboring switching patterns. Therefore, this approach can be easily implemented into existing timing analysis flows such as max-timing and min-timing analysis. Finally, we apply the new modeling approach to a range of activities across the design process including timing optimization, static timing analysis, high frequency clock design, and data-bus wire planning.