A sparse image method for BEM capacitance extraction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
IC analyses including extracted inductance models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Virtual screening: a step towards a sparse partial inductance matrix
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On the impact of on-chip inductance on signal nets under the influence of power grid noise
Proceedings of the conference on Design, automation and test in Europe
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Modeling magnetic coupling for on-chip interconnect
Proceedings of the 38th annual Design Automation Conference
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
A solenoidal basis method for efficient inductance extraction
Proceedings of the 39th annual Design Automation Conference
On the efficacy of simplified 2D on-chip inductance models
Proceedings of the 39th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Implicit treatment of substrate and power-ground losses in return-limited inductance extraction
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A local circuit topology for inductive parasitics
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A precorrected-FFT method for simulating on-chip inductance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On-chip interconnect modeling by wire duplication
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Robust and passive model order reduction for circuits containing susceptance elements
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
Electrical Modeling of Integrated-Package Power and Ground Distributions
IEEE Design & Test
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
SCORE: SPICE COmpatible Reluctance Extraction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
CHIME: coupled hierarchical inductance model evaluation
Proceedings of the 41st annual Design Automation Conference
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SPICE compatible circuit models for partial reluctance K
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Spatially distributed 3D circuit models
Proceedings of the 42nd annual Design Automation Conference
Partial reluctance based circuit simulation is efficient and stable
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Generating stable and sparse reluctance/inductance matrix under insufficient conditions
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
Speeding Up PEEC partial inductance computations using a QR-based algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switch-factor based loop RLC modeling for efficient timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the impact of on-chip inductance on signal nets under the influence of power grid noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
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This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding the smallest matrix terms, the proposed approach maintains accuracy at middle and high frequencies and is guaranteed to be positive definite for any degree of sparsity (thereby producing stable circuit solutions). While the proposed technique is strictly based upon potential theory (i.e. the invariance of potential differences on the zero potential reference choice), the technique is, nevertheless, presented and discussed in both circuit and magnetic terms. The conventional and the proposed sparse formulation techniques are contrasted in terms of eigenvalues and circuit simulation results on practical examples.