Accelerated modeling of massively coupled RLC interconnects using the relative inductance extraction method

Authors:
Kaveh Shakeri;James D. Meindl
Affiliations:
Cypress Semiconductor, San Jose, CA;Microelectronics, Georgia Institute of Technology, Atlanta, GA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

A new inductance extraction method is defined to accelerate modeling of massively coupled resistance-inductance-capacitance (RLC) interconnects. The new relative inductance generates a sparse inductance matrix. Therefore, it enables modeling of large circuits with reasonable speed and accuracy. It maintains accuracy for a wide frequency range, even for the cases that there are far inductance couplings. It is demonstrated that the relative inductance matrix is equivalent to the conventional partial inductance matrix. Simulations done for a 16-bit bus with each bus line divided into 32 segments show that the simulations using the relative inductance method is 20 times faster and requires 9.5 times less memory compared to the established partial inductance method.