FastHenry: a multipole-accelerated 3-D inductance extraction program

Preservation of passivity during RLC network reduction via split congruence transformations

DAC '97 Proceedings of the 34th annual Design Automation Conference

Interconnect analysis: from 3-D structures to circuit models

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

An efficient algorithm for fast parasitic extraction and passive order reduction of 3D interconnect models

Proceedings of the conference on Design, automation and test in Europe

INDUCTWISE: inductance-wise interconnect simulator and extractor

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

A precorrected-FFT method for simulating on-chip inductance

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures

EDTC '95 Proceedings of the 1995 European conference on Design and Test

SCORE: SPICE COmpatible Reluctance Extraction

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Frequency-dependent reluctance extraction

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Accelerated modeling of massively coupled RLC interconnects using the relative inductance extraction method

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Speeding Up PEEC partial inductance computations using a QR-based algorithm

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Clock-tree synthesis for low-EMI design

Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics

Differential current-sensing for on-chip interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient optimization of fully-integrated inductive DC---DC converters comprising tapered inductor layout synthesis and temperature effects

Analog Integrated Circuits and Signal Processing