An efficient algorithm for fast parasitic extraction and passive order reduction of 3D interconnect models

Authors:
N. Marques;M. Kamon;J. White;L. M. Silveira
Affiliations:
INESC/Cadence European Laboratories, Dept. of Electrical and Computer Engineering, Instituto Superior Técnico, 1000 Lisboa, Portugal;Research Laboratory of Electronics, Dept. of Electrical Eng. and Comp. Science, Massachusetts Institute of Technology, Cambridge, MA;Research Laboratory of Electronics, Dept. of Electrical Eng. and Comp. Science, Massachusetts Institute of Technology, Cambridge, MA;INESC/Cadence European Laboratories, Dept. of Electrical and Computer Engineering, Instituto Superior Técnico, 1000 Lisboa, Portugal
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

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Abstract

As VLSI circuit speeds have increased, the need for accurate three-dimensional interconnect models has become essential to accurate chip and system design. In this paper, we describe an integral equation approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling along conductors. Unlike previous methods, our approach is based on a modified nodal analysis formulation and can be used directly to generate guaranteed passive low order interconnect models for efficient inclusion in a standard circuit simulator