FastHenry: a multipole-accelerated 3-D inductance extraction program
DAC '93 Proceedings of the 30th international Design Automation Conference
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Digital systems engineering
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
On-chip inductance issues in multiconductor systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Proceedings of the 39th annual Design Automation Conference
Optimum wire sizing of RLC interconnect with repeaters
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Transition Aware Global Signaling (TAGS)
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Current Sensing Techniques for Global Interconnects in Very Deep Submicron(VDSM) CMOS
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater and current-sensing hybrid circuits for on-chip interconnects
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Current-sensing and repeater hybrid circuit technique for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling of energy dissipation in RLC current-mode signaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise.