Delay and Power Expressions for a CMOS Inverter Drivinga Resistive-Capacitive Load
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Interconnect accelerating techniques for sub- 100-nm gigascale systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Simultaneous shield and repeater insertion
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Resource based optimization for simultaneous shield and repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The concept of a “transparent repeater1,” which is an amplifier circuit designed to minimize the delay introduced by highly resistive interconnect lines in high speed digital circuits, is introduced and described in this paper. An insertion methodology for this circuit is also discussed. Defining characteristics of this circuit are: the input is connected to the output, the output generates the same sense transition as the corresponding input transition, the buffer output becomes high impedance after every transition, and the buffer may detect input transitions with low threshold voltages.