Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power dissipated by CMOS gates driving lossless transmission lines
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Resistive Power in CMOS Circuits
Analog Integrated Circuits and Signal Processing
Integration, the VLSI Journal
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools
Microelectronics Journal
| Hi-index | 0.00 |
A delay and power model of a CMOS inverter driving aresistive-capacitive load is presented. The model is derivedfrom Sakurai‘s alpha-power law and exhibits good accuracy. Themodel can be used to design and analyze those CMOS invertersthat drive a large RC load when considering bothspeed and power. Expressions are provided for estimating thepropagation delay and transition time which exhibit less than27% discrepancy from SPICE for a wide variety of RCloads. Expressions are also provided for modeling the short-circuitpower dissipation of a CMOS inverter driving a resistive-capacitiveinterconnect line which are accurate to within 15% of SPICEfor most practical loads.