Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Delay and Power Expressions for a CMOS Inverter Drivinga Resistive-Capacitive Load
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient Gate Delay Modeling for Large Interconnect Loads
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy consumption in RC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic waveform evaluation for timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay and current estimation in a CMOS inverter with an RC load
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect-aware low-power high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, models of input admittance of RC interconnects are discussed in depth to understand and evaluate their loading effects on driving CMOS gates. From a detailed analysis of input admittance pole-zero location, arguments are derived to prove that their input admittance can be accurately approximated to that of a low-order equivalent RC circuit, in contrast to the case of timing analysis of RC wires. More specifically, 1st- or 2nd-order equivalent circuits are derived analytically via the moment matching approach, in contrast to previous analyses that rely on purely numerical approaches. Moreover, simple analytical rules to extend results to arbitrarily complex networks are derived, as opposed to the usual approach that requires numerical estimation of moments. Being fully analytical, the proposed approach permits one to develop models that are extremely simple (i.e. computationally efficient), as well as to gain an insight into the properties of input admittance of RC interconnects. The proposed equivalent circuits are evaluated and validated in situations that occur in real CAD design flows, where RC wire loading effects are estimated by CAD tools to perform the timing/power analysis of the buffer driving the wire. The analysis is validated through extensive simulations on a 65nm CMOS technology. Well-defined criteria are also derived to select the appropriate model of RC wire input admittance for accurate timing/power estimations in VLSI CAD tools.