Modeling of Propagation Delay of a First Order Circuit with a Ramp Input
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
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Proceedings of the 40th annual Design Automation Conference
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Minimize the delay of parasitic capacitance and modeling in RLC circuit
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Microelectronics Journal
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A novel and efficient method is presented for computing the delay and supply current pulse in a CMOS inverter with an RC load. The method builds on existing techniques for computing these quantities in the presence of a capacitance load. As in the work of other authors, the concept of an effective capacitance Ceff is used. However, here it captures the inverter's behavior only while the charging/discharging transistor is in saturation and, therefore, behaves like a current source to a good approximation. This capacitance is determined by means of a simple iterative procedure that uses an empirical piecewise-linear approximation to the RC circuit's output voltage, which has a normal CMOS symmetrical form. Since a Ceff defined in the above way is independent of the inverter's parameters, such as transistor size, the coefficients of the approximation have to be determined for only one reference inverter. A simple analytical method yields the inverter's output voltage outside the saturation region. The complete model has been shown to be accurate for both 0.8-μm 5-V and 0.24-μm 2.5-V CMOS technologies. Its speed is comparable to that of the “capacitance load” techniques that it relies on