Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microelectronic Circuit Analysis and Design
Microelectronic Circuit Analysis and Design
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Delay and current estimation in a CMOS inverter with an RC load
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper shows that how to minimize the delay. We changed several elements to minimize the delay in the circuit. Simulation results show the best effect when the value of parasitic capacitance is changed. We found eligible point by simulating Parasitic Capacitance case by case based and proved it. Types of case are Elmore delay, Interconnection delay, lowering Parasitic Capacitance's parameter entirely, raising Parasitic Capacitance's parameter in order of precedence, lowering Parasitic Capacitance's parameter in order of precedence, and changing inverter's W parameter. And it has been apparently proven that case of using parasitic capacitance is better than other methods.