On wirelength estimations for row-based placement
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Shielding effect of on-chip interconnect inductance
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Efficient Macromodeling for On-Chip Interconnects
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement
Journal of VLSI Signal Processing Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Integration, the VLSI Journal
Fast bus waveform estimation at the presence of coupling noise
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools
Microelectronics Journal
Shielding effect of on-chip interconnect inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient delay metric on RC interconnects under saturated ramp inputs
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV
| Hi-index | 0.00 |
With fast switching speeds and large interconnect trees (MCMs), the resistance and inductance of interconnect has a dominant impact on logic gate delay. In this paper, we propose a new PI model for distributed RC and RLC interconnects to estimate the driving point admittance at the output of a CMOS gate. Using this model we are able to compute the gate delay efficiently, within 25% of SPICE-computed delays. Our parameters depend only on total interconnect tree resistance and capacitance at the output of the gate. Previous ``effective load capacitance'' methods, applicable only for distributed RC interconnects, are based on PI model parameters obtained via a recursive admittance moment computation. Our model should be useful for iterative optimization of performance-driven routing or for estimation of gate delay and rise times in high-level synthesis.