A unified design methodology for CMOS tapered buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of RC interconnections under ramp input
DAC '96 Proceedings of the 33rd annual Design Automation Conference
New efficient algorithms for computing effective capacitance
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Realizable reduction for RC interconnect circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient analytical model of coupled on-chip RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An "effective" capacitance based delay metric for RC interconnect
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Shielding effect of on-chip interconnect inductance
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Efficient Gate Delay Modeling for Large Interconnect Loads
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Analysis of on-chip inductance effects for distributed RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire shaping of RLC interconnects
Integration, the VLSI Journal
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Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.