DAC '96 Proceedings of the 33rd annual Design Automation Conference
An accurate and efficient gate level delay calculator for MOS circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A new framework for static timing analysis, incremental timing refinement, and timing simulation
ATS '00 Proceedings of the 9th Asian Test Symposium
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A modeling technique for CMOS gates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timed pattern generation for noise-on-delay calculation
Proceedings of the 39th annual Design Automation Conference
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
Journal of Electronic Testing: Theory and Applications
TA-PSV—Timing Analysis for Partially Specified Vectors
Journal of Electronic Testing: Theory and Applications
Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Low power ATPG for path delay faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low power test generation for path delay faults using stability functions
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Algorithms for MIS vector generation and pruning
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical gate delay model for multiple input switching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Analytical model for the impact of multiple input switching noise on timing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
A current source model for CMOS logic cells considering multiple input switching and stack effect
Proceedings of the conference on Design, automation and test in Europe
Worst-case aggressor-victim alignment with current-source driver models
Proceedings of the 46th Annual Design Automation Conference
Timed input pattern generation for an accurate delay calculation under multiple input switching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shielding effect of on-chip interconnect inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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