DAC '96 Proceedings of the 33rd annual Design Automation Conference
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Probabilistic interval-valued computation: representing and reasoning about uncertainty in dsp and vlsi design
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
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The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriving at different inputs causes significant variation in the gate delay. This variation in delay affects the accuracy of our timing estimates. In this paper, we derive simple analytical models for incorporating the effect of simultaneous multiple input switching events on gate delay. The model presented requires minimum additional characterization effort, and can be employed in a statistical timing engine. The dynamic delay variability of a path caused by MIS noise can be accurately estimated using the proposed model.